The present invention relates to the field of manufacturing semiconductor devices and, more particularly, to an improved salicide process of forming metal silicide contacts.
An important aim of ongoing research in the semiconductor industry is the reduction in the dimensions of the devices used in integrated circuits. Planar transistors, such as metal oxide semiconductor (MOS) transistors, are particularly suited for use in high-density integrated circuits. As the size of the MOS transistors and other active devices decreases, the dimension the size of the source/drain regions and gate electrodes, and the channel region of each device, decrease correspondingly.
The design of ever-smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junctions. Shallow junctions are necessary to avoid lateral diffusion of implanted dopants into the channel, since such a diffusion disadvantageously contributes to leakage currents and poor breakdown performance. Shallow source/drain junctions, for example on the order of 1,000 xc3x85 or less thick are generally required for acceptable performance in short channel devices.
Metal silicide contacts are typically used to provide low resistance contacts to source/drain regions and gate electrodes. The metal silicide contacts are conventionally formed by depositing a conductive metal, such as titanium, cobalt, tungsten, or nickel, on the source/drain regions and gate electrodes by physical vapor deposition (PVD), e.g. sputtering or evaporation; or by a chemical vapor deposition (CVD) technique. Subsequently, heating is performed to react the metal with underlying silicon to form a metal silcide layer on the source/drain regions and gate electrodes. The metal silicide has a substantially lower sheet resistance than the silicon to which it is bonded. Selective etching is then conducted to remove unreacted metal from the non-silicided areas, such as the dielectric sidewall spacers. Thus, the silicide regions are aligned only on the electrically conductive areas. This self-aligned silicide process is generally referred to as the xe2x80x9csalicidexe2x80x9d process.
A portion of a typical semiconductor device 40 is schematically illustrated in FIG. 1A and comprises a silicon-containing substrate 10 with source/drain regions 34 formed therein. Gate oxide layer 14 and gate electrode 16 are formed on the silicon-containing substrate 10. Sidewall spacers 30 are formed on opposing side surfaces 18 of gate electrode 16. Sidewall spacers 30 typically comprise silicon based insulators, such as silicon nitride, silicon oxide, or silicon carbide. The sidewall spacers 30 mask the side surfaces 18 of the gate 16 when metal layer 36 is deposited, thereby preventing silicide from forming on the gate electrode side surfaces 18.
After metal layer 36 is deposited, heating is conducted at a temperature sufficient to react the metal with underlying silicon in the gate electrode 16 and substrate surface 12 to form conductive metal silcide contacts 38 (FIG. 1B). After the metal silcide contacts 38 are formed, the unreacted metal 36 is removed by etching, as with a wet etchant, e.g., an aqueous H2O2/NH4OH solution. The sidewall spacer 30, therefore, functions as an electrical insulator separating the silicide contact 38 on the gate electrode 16 from the metal silicide contacts 38 on the source/drain regions 34, as shown in FIG. 1B.
Various metals react with Si to form a silicide, however, titanium (Ti) and cobalt (Co) are currently the most common metals used to create silcides (TiSi2, CoSi2) when manufacturing semiconductor devices utilizing salicide technology.
Use of a TiSi2 layer imposes limitations on the manufacture of semiconductor devices. A significant limitation is that the sheet resistance for lines narrower than 0.35 micrometers is high, i.e., as TiSi2 is formed in a narrower and narrower line, the resistance increases. Another significant limitation is that TiSi2 initially forms a high resistivity phase (C49), and transformation from C49 to a low resistivity phase (C54) is nucleation limited, i.e., a high temperature is required to effect the phase change.
Cobalt silicide, unlike TiSi2, exhibits less linewidth dependence of sheet resistance. However, CoSi2 consumes significant amounts of Si during formation, which increases the difficulty of forming shallow junctions. Large Si consumption is also a concern where the amount of Si present is limited, for example, with silicon on insulator (SOI) substrates. Without enough Si to react with Co to form CoSi2, a thin layer of CoSi2 results. The thickness of the silicide layer is an important parameter because a thin silicide layer is more resistive than a thicker silicide layer of the same material; thus a thicker silicide layer increases semiconductor device speed, while a thin silicide layer reduces device speed.
Recently, attention has turned towards using nickel to form NiSi utilizing salicide technology. Using NiSi is advantageous over using TiSi2 and CoSi2 because many limitations associated with TiSi2 and CoSi2 are avoided. When forming NiSi, a low resistivity phase is the first phase to form, and does so at a relatively low temperature. Additionally, nickel (Ni), like Co, diffuses through the film into Si, unlike Ti where the Si diffuses into the metal layer. Diffusion of Ni and Co through the film into Si prevents bridging between the silicide layer on the gate electrode and the silicide layer over the source/drain regions. The reaction that forms NiSi requires less Si than when TiSi2 and CoSi2 are formed. Nickel silicide exhibits almost no linewidth dependence of sheet resistance. Nickel silcide is normally annealed in a one step process, versus a process requiring an anneal, an etch, and a second anneal, as is normal for TiSi2 and CoSi2. Nickel silicide also exhibits low film stress, i.e., causes less wafer distortion.
In addition to the annealing step to form the silicide, there are additional high temperature heating steps in conventional MOS semiconductor device fabrication processes. Conventional processes also require one or more high temperature annealing steps to activate the source/drain regions and source/drain extensions. For example, in addition to the anneal at greater than 1,000xc2x0 C. to activate the source/drain dopants, the formation of devices with CoSi2 contacts requires a two-step annealing process which includes a first annealing at approximately 500xc2x0 C. and a second annealing at approximately 800xc2x0 C. Multiple high temperature heat treatment steps increase the manufacturing costs and the complexity of semiconductor device fabrication. High temperature annealing increases lateral and vertical diffusion of the dopants in the source/drain regions. Increased vertical diffusion of dopant results in slower, deeper junctions, while increased lateral diffusion of the dopant can result in junction leakage. Furthermore, every time a wafer is heated and cooled crystal damage from dislocations occur. A high concentration of dislocations can cause device failure from leakage currents.
The term semiconductor devices, as used herein, is not to be limited to the specifically disclosed embodiments. Semiconductor devices, as used herein, include a wide variety of electronic devices including flip chips, flip chip/package assemblies, transistors, capacitors, microprocessors, random access memories, etc. In general, semiconductor devices refer to any electrical device comprising semiconductors.
There exists a need in the semiconductor device manufacturing art to provide a process for forming metal silicide contacts for planar transistors with fewer high temperature annealing steps. There exists a need in this art to implant dopant in the source/drain regions without requiring a high temperature anneal to activate the dopants. There exists a need in this art to provide doped source/drain regions with metal siuicide contacts manufactured by a process requiring only one relatively low temperature anneal.
These and other needs are met by the embodiments of the present invention, which provide a method of manufacturing a semiconductor device comprising providing a silicon-containing semiconductor substrate having an upper surface and a gate electrode formed on the upper surface of the substrate with a gate insulating layer therebetween. The gate electrode has an upper surface and opposing side surfaces. Selected regions of the semiconductor substrate are made amorphous. Source/drain regions are formed in the amorphous regions by doping the semiconductor substrate with a dopant. A metal layer is subsequently deposited over the semiconductor substrate and the substrate is annealed, by a single heating step, to simultaneously activate the source/drain regions and to react the metal layer with silicon in the gate electrode and source/drain regions to form metal silicide contacts.
The earlier stated needs are also met by other embodiments of the present invention that provide a semiconductor device having a silicon-containing semiconductor substrate having an upper surface and a gate electrode formed on the upper surface with a gate insulating layer therebetween. The gate electrode has an upper surface and opposing side surfaces. Metal silicide contacts are formed on the upper surface of the gate electrode and over source/drain regions in the substrate that were formed by doping amorphous regions of the substrate.
The earlier stated needs are further met by other embodiments of the instant invention that provide a method of manufacturing a semiconductor device by activating dopants and forming silicide contacts on the device with a single annealing step comprising providing a silicon-containing semiconductor substrate. A gate oxide layer and a conductive gate material layer are, in turn, formed over the semiconductor substrate. The gate material layer and gate oxide layer are patterned to form a gate electrode having an upper surface and opposing side surfaces with a gate oxide layer below the gate electrode. Selected regions of the substrate are made amorphous by ion implanting a dopant into the selected regions of the substrate. Source/drain extensions are formed by ion implanting a dopant into the amorphous regions of the substrate. A layer of insulating material is deposited over the gate electrode and the semiconductor substrate and the insulating material is patterned to form sidewall spacers on the opposing side surfaces of the gate electrode. Source/drain regions are then formed by ion implanting a dopant into the amorphous regions. A metal layer is subsequently deposited on the upper surface of the gate electrode, the sidewall spacers, and the source/drain regions. The semiconductor substrate is annealed at a temperature sufficient to activate the source/drain regions and to cause the metal layer to react with silicon in the gate electrode and source/drain regions to form metal silicide contacts. Subsequently, the unreacted metal that did not form metal silicide is removed
This invention addresses the need of an improved method of manufacturing semiconductor devices, with high conductivity silicide contacts on the source/drain regions and gate electrode, with fewer high temperature annealing steps. This invention reduces the possibility of semiconductor device crystal damage and junction leakage. This invention provides an economical manufacturing method requiring fewer heating step.
The foregoing and other features, aspects, and advantages of the present invention will become apparent in the following detailed description of the present invention when taken in conjunction with the accompanying drawings.